1. Field of the Invention
The present invention relates to voltage level shifter circuits and, more particularly, to a voltage level shifter circuit that controls voltage levels of a clock signal and an inverted clock signal for driving gate lines of a liquid crystal display panel.
2. Description of the Related Art
A small thin film transistor liquid crystal display (TFT-LCD), which is generally applied to a portable display such as a mobile communications terminal, includes a source driver that drives sources lines, a gate driver that drives gate lines, and a power integrated circuit that provides power voltages to the liquid crystal display panel, where the source and gate drivers use charge pumping.
FIG. 1 shows the structure of an amorphous silicon gate (ASG) panel, indicated generally by the reference numeral 100. Referring to FIG. 1, the ASG panel 100 has a gate driver 110 formed in amorphous silicon. Thus, the number of external components of the display panel 100 is low to save costs.
FIG. 2 shows the configuration of the gate driver of FIG. 1, indicated generally by the reference numeral 110. Referring to FIG. 2, the gate driver 110 of the ASG panel includes a plurality of shift registers SR1, SR2, SR3 and SR4 that sequentially turn on gate lines G1, G2, G3 and G4, respectively, in response to a clock signal CKV and an inverted clock signal CKVB.
When a start pulse STV drives the first shift register SR1, the first shift register SR1 turns on the first gate line G1 in response to the clock signal CKV. The turned on first gate line G1 drives the second shift register SR2, and the second shift register SR2 turns on the second gate line G2 in response to the inverted clock signal CKVB. The turned on second gate line G2 drives the third shift register SR3 and, simultaneously, turns off the first shift register SR1. In this manner, the gate lines G1, G2, G3 and G4 are sequentially turned on.
The odd-numbered shift registers including the first and third shift registers SR1 and SR3 are operated in synchronization with the clock signal CKV whereas the even-numbered shift registers including the second and fourth shift registers SR2 and SR4 are operated in synchronization with the inverted clock signal CKVB. This is for increasing a speed of turning on the gate lines G1, G2, G3 and G4.
A gate driver of a general liquid crystal display is provided in an external driver unit of the display panel. The liquid crystal display includes level shifters as many as shift registers of the gate driver in order to generate a voltage for driving the shift registers.
However, the ASG panel 100 has the gate driver 110 included therein, as shown in FIG. 1. Accordingly, level shifters (not shown) that supply the clock signal CKV, inverted clock signal CKVB, and start pulse STV to the gate driver 110 and control voltage levels of the clock signal CKV, inverted clock signal CKVB and start pulse STV are provided in an external driver installed outside the panel 100.
While the conventional liquid crystal display requires level shifters numbering as many as the shift registers, the driver (not shown) that drives the ASG panel 100 includes only three level shifters that provide the clock signal CKV, inverted clock signal CKVB and start pulse STV.
FIG. 3 shows the configuration of a conventional level shifter circuit, indicated generally by the reference numeral 300. The conventional level shifter circuit 300 generates the signals for driving the gate driver 110 of FIG. 2. Referring to FIG. 3, the level shifter circuit 300 includes first, second and third level shifters 310, 320 and LS1.
The first level shifter 310 generates the clock signal CKV in response to a clock-activating signal CL, and the second level shifter 320 generates the inverted clock signal CKVB in response to an inverted clock-activating signal SFTCLK. The third level shifter LS1 generates the start pulse STV in response to a frame-driving signal FLM.
The first, second and third level shifters 310, 320 and LS1 receive a select signal GLS. The level shifter circuit 300 is installed at two points in the driver (not shown) in consideration of positions of the driver and panel, which is not shown in FIG. 3.
The select signal GLS selects one of the two level shifter circuits installed in the driver. Thus, the level shifter circuit 300 of FIG. 3 is operated when the select signal GLS has a high level.
A level shifting logic LS2 of the first level shifter 310 amplifies a voltage level of the clock-activating signal CL, and inverts a logic level of the clock-activating signal CL. When the clock-activating signal CL has a high level, the level shifting logic LS2 and inverters INV1 and INV2 output the clock-activating signal CL having a low level. Then, a first transistor TR1 is turned on and a second transistor TR2 is turned off. Accordingly, the voltage level of the clock signal CKV is increased to a positive external voltage VGH.
When the clock-activating signal CL has a low level, the second transistor TR2 is turned on and the first transistor TR1 is turned off. Thus, the voltage level of the clock signal CKV is decreased to a negative external voltage VGOFFOUT.
As described above, the clock activating signal CL is output as the clock signal CKV that swings between the positive external voltage VGH and negative external voltage VGOFFOUT according to the first level shifter 310.
The second level shifter 320 receives the inverted clock activating signal SFTCLK and outputs the inverted clock signal CKVB that swings between the positive external voltage level VGH and negative external voltage level VGOFFOUT.
Amorphous silicon in which the gate driver 110 of the ASG panel 100 is formed has a low mobility and poor on/off characteristic. Thus, a level shifter circuit that makes the clock signal CKV, inverted clock signal CKVB and start pulse STV have a wide swing range of −10V to +15V is required in order to drive the gate driver 110. In the case of the portable display such as a mobile communication terminal, a voltage level of −10V to +15V is obtained by boosting or dropping a battery voltage using a charge pump circuit.
When a voltage generated using the level shifter circuit 300 is used to drive gate lines, current consumption is increased in proportion to a voltage level boosted or dropped in the level shifter circuit 300 and the swing range of the level shifter circuit 300.
The quantity of current consumed by the level shifter circuit 300 installed in the driver (not shown) to drive the gate driver 110 of the ASG panel 100 is determined by I=C*V*f. Here, C is a load of gate lines, V is a swing range of the level shifter, and f is an operating frequency.
To generate a clock signal CKV having a positive external voltage level VGH of 15V for example, when a battery voltage is 2.5V, the voltage level 2.5V should be boosted six times using a charge pump circuit. In this case, the quantity of current consumed when the voltage level of the clock signal CKV is boosted from the negative external voltage level VGOFFOUT to the positive external voltage level VGH is increased six times.
That is, the first and second level shifters 310 and 320 of the conventional level shifter circuit 300 that generates the clock signal CKV and inverted clock signal CKVB drive the entire gate lines of the ASG panel 100 so that the quantity of current consumed by the conventional level shifter circuit 300 is undesirably high.